1. Field of the Invention
This invention relates to a flip-flop, an integrated circuit using the same, and a flip-flop resetting method capable of resetting a flip-flop (hereinafter referred to as FF) by changing a power supply voltage.
2. Description of the Related Art
Conventionally, there are known a variety of techniques of resetting an FF. For example, as an integrated circuit capable of initializing an FF included therein, there is known an integrated circuit including: a selection signal sending section that sends a selection signal for a predetermined time period after power-on of the integrated circuit; a first selection section that sends a logic signal of a certain level to a master set terminal when the selection signal is sent, and sends an original logic signal to the master set terminal when the selection signal is not sent; and a second selection section that sends a logic signal having an inverse value of the logic signal of the certain level to the master set terminal when the selection signal is sent, and sends the original logic signal to the master set terminal when the selection signal is not sent. (refer to Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2-100413).
As described above, the conventional FF is designed to reset its data. As described above, however, to reset the data of the FF, it is necessary to provide a reset terminal in the FF for distributing a reset signal in an integrated circuit (e.g., an LSI), for example. Therefore, a wiring in the LSI is complicated. Further, space for wiring a reset signal line is required, and thus there is a limit in adding other signal wirings. As a result, it becomes difficult to increase the number of channels used for a signal wiring.